Electrical circuits may experience diminished performance due to parasitic capacitances associated with their components. For example, in power amplifiers used in wireless communication applications, parasitic capacitances may reduce the gain of radio frequency (RF) signals, resulting in detuning at an input due to output load variations and also in potential instability. To counteract parasitic capacitances, some circuits include so-called neutralization capacitances that produce a neutralization current to effectively cancel signals produced by the parasitic capacitances.
FIG. 1 is a diagram of a conventional differential amplifier 100 comprising neutralization capacitances. Differential amplifier 100 may be used as a power amplifier in communication applications and other contexts.
Referring to FIG. 1, differential amplifier 100 comprises first and second metal oxide semiconductor (MOS) transistors M1 and M2 having respective gates receiving a differential pair of input signals IN+ and IN−, respective drains receiving a differential pair of output signals OUT− and OUT+, and respective sources connected to ground. During typical operation, differential amplifier 100 receives the differential pair of input signals IN+ and IN−, and it amplifies those signals to produce the differential pair of output signals OUT+ and OUT−.
A parasitic capacitance Cgd between the gate and drain of each of first and second MOS transistors M1 and M2 provides a feedback path that results in poor isolation between input and output, reduces the gain of differential amplifier 100, and reduces the power efficiency of differential amplifier 100. This feedback phenomenon and its consequences are commonly referred to as the Miller effect.
To counteract the Miller effect, differential amplifier 100 further comprises first and second differential neutralization capacitances Cdn1 and Cdn2, which are cross-coupled between the input and output terminals as shown in the figure. These capacitors allow a compensation current to flow between the terminals, which tends to cancel the feedback. The provision of this current is referred to as differential neutralization. In a differential sense, the presence of differential neutralization capacitances ideally reduce gate-to-drain capacitance to zero. In a common mode sense, the presence of differential neutralization capacitances effectively doubles the gate-to-drain capacitance.
Some potential benefits of differential neutralization in the illustrated context include isolation of input and output signals, which tends to simplify design, stabilization of differential amplifier 100 for any passive impedance at its inputs and outputs, and rendering the differential input impedance independent of any output load.
FIG. 2 is a diagram of a conventional H-bridge circuit 200 comprising differential neutralization capacitances. This diagram is presented as another example application of the differential neutralization concept.
Referring to FIG. 2, H-bridge circuit 200 comprises first and second negative channel MOS (NMOS) transistors N1 and N2, first and second positive channel MOS (PMOS) transistors P1 and P2, and differential neutralization capacitances Cdnp and Cdnn. A first pair of differential neutralization capacitances Cdnn neutralizes intrinsic gate-to-drain capacitances of an NMOS gain stage formed by NMOS transistors N1 and N2. A second pair of differential neutralization capacitances Cdnp neutralizes intrinsic gate-to-drain capacitances of a PMOS gain stage formed by PMOS transistors P1 and P2. In the example of FIG. 2, an effective gate-to-drain capacitance can be derived for a hybrid-pi small signal model of each gain stage.
In a differential mode sense, the effective Miller capacitance of H-bridge circuit 200 can be equal to zero when Cdn=Cgd, i.e., where the overall differential neutralization capacitance is equal to the gate-to-drain capacitance. Under such a condition, H-bridge circuit 200 may be stable for all passive source and load terminations.
Using the hybrid-pi small signal model, the following parameters of H-bridge circuit 200 can be characterized by the following equations (1)-(4): differential input admittance (Yin, dd), differential output admittance (Yout, dd), common mode input admittance (Yin, cc), and common mode output admittance (Yout, cc).
                              Y          in                ,                  dd          =                                    1              2                        ⁡                          [                                                Y                  gs                                +                                  Y                  gd                                +                                  Y                  x                                +                                                                            (                                                                        Y                          x                                                -                                                  Y                          gd                                                                    )                                        ⁢                                          (                                                                        g                          m                                                -                                                  Y                          gd                                                +                                                  Y                          x                                                                    )                                                                                                  Y                      ds                                        +                                          Y                      gd                                        +                                          Y                      x                                                                                  ]                                                          (        1        )                                          Y          out                ,                  dd          =                                    1              2                        ⁡                          [                                                Y                  ds                                +                                  Y                  gd                                +                                  Y                  x                                +                                                                            (                                                                        Y                          x                                                -                                                  Y                          gd                                                                    )                                        ⁢                                          (                                                                        g                          m                                                -                                                  Y                          gd                                                +                                                  Y                          x                                                                    )                                                                                                  Y                      gs                                        +                                          Y                      gd                                        +                                          Y                      x                                                                                  ]                                                          (        2        )                                          Y          in                ,                  cc          =                      2            ⁡                          [                                                Y                  gs                                +                                  Y                  gd                                +                                  Y                  x                                +                                                                            (                                                                        Y                          x                                                +                                                  Y                          gd                                                                    )                                        ⁢                                          (                                                                        g                          m                                                -                                                  Y                          gd                                                -                                                  Y                          x                                                                    )                                                                                                  Y                      ds                                        +                                          Y                      gd                                        +                                          Y                      x                                                                                  ]                                                          (        3        )                                          Y          out                ,                  cc          =                      2            ⁡                          [                                                Y                  ds                                +                                  Y                  gd                                +                                  Y                  x                                +                                                                            (                                                                        Y                          x                                                +                                                  Y                          gd                                                                    )                                        ⁢                                          (                                                                        g                          m                                                -                                                  Y                          gd                                                -                                                  Y                          x                                                                    )                                                                                                  Y                      gs                                        +                                          Y                      gd                                        +                                          Y                      x                                                                                  ]                                                          (        4        )            
In equations (1)-(4) for the hybrid-pi equivalent, Ygs denotes gate-to-source admittance of a single device including any external source admittance. Ygd denotes gate to drain (Miller) admittance for a single device. Yds denotes drain-to-source admittance of a single device including any external load admittance. Yx denotes admittance of one differential neutralization capacitor. gm denotes transconductance of a single device.
In the examples of FIGS. 1 and 2, neutralization capacitances are typically implemented by metal capacitors (e.g., sidewall and overlap capacitors) or metal-insulator-metal (MIM) capacitors. These capacitors provide potential benefits in that they are mostly bias independent. In other words, they do not have a high sensitivity to a drain-source voltage Vds or gate-drain voltage Vgd of the MOS devices. Accordingly, once the differential neutralization capacitances are appropriately implemented by metal or MIM capacitors, they tend to work well across different supply levels and bias conditions. A potential drawback of these capacitors, however, is that they do not track Cgd of the MOS devices very well with process variations and die-to-die and lot-to-lot variations. This is because Cgd of the MOS devices is determined by overlap capacitance (assuming the device is in saturation mode), which can vary significantly with small variations in the thickness of an oxide layer. Meanwhile, the metal or MIM capacitors do not have a commensurate variation according to the thickness of the oxide layer, so they may not be appropriately matched to Cgd from die-to-die or lot-to-lot.
Accordingly, in view of these and other shortcomings of conventional technologies, there is a general need for new approaches to differential neutralization in certain contexts.